This invention relates to methods and circuits for high-speed, high-resolution comparator architectures. More particularly, this invention relates to comparator architectures with latch offset cancellation and coupling capacitor sharing techniques.
Comparator circuits, including amplify-and-latch circuit architectures, are well known. Such circuits can be used to determine the amplitude of signals with respect to common voltage references, or to compare the relative amplitude of two signals. Comparators are especially useful for making digital approximations of analog signals in analog-to-digital converter circuits. When included as part of an analog-to-digital converter design, the speed and resolution of comparators have crucial influences on the overall speed and resolution of the circuit.
A single stage comparator architecture includes a preamplifier stage electrically coupled to a latch. The preamplifier stage samples the voltage difference established at its input, and outputs an amplified difference. The latch serves the dual purpose of digitizing the amplified analog signal at its input to produce a logic level at its output, and sampling the amplified signal to produce a clocked sample of the input signal at its output.
The performance of comparator circuits may be evaluated in terms of bandwidth, power consumption, and resolution. In typical comparator designs, these performance criteria may be traded-off against each other. For example in a single-stage comparator design, the bandwidth of the comparator may be increased at the cost of decreasing the resolution of the comparator or increasing the power consumption of the comparator.
The resolution of a comparator may be limited by the offset voltage of the comparator. The offset voltage may impose an upper limit on the performance of a comparator by preventing the comparator from accurately measuring potential differences smaller than the offset voltage. Switching capacitor circuits may be used to compensate for the offset voltage of the comparator in order to increase the resolution of the comparator. However, the use of switching capacitor circuits may limit the bandwidth of a comparator because of the capacitive loading caused by the switching capacitors. The use of switching capacitor circuits may also produce switching noise including charge injection noise in the circuit, thereby limiting the resolution of the comparator. Switching capacitor circuits may also be expensive to produce because of the additional circuitry they require and the large silicon area required for the fabrication of integrated circuit capacitors.
It would be desirable to have comparator circuit architectures and methods for operating comparator circuits that are able to provide improved performance of comparator circuits. It would therefore also be desirable to provide circuitry for a high-speed, high-resolution comparator that implements latch offset cancellation and a coupling capacitor sharing technique.